1. Field of Invention
The present invention relates to a semiconductor device including a ferroelectric capacitor and a method for manufacturing the same.
2. Description of Related Art
In recent years, a cross-point FeRAM has drawn attention as a semiconductor device having ferroelectric capacitors. In the cross-point FeRAM, upper electrode layers are arrayed in columns and lower electrode layers are arrayed in rows so as to be laid out in a matrix, and a plurality of ferroelectric capacitors are provided at each intersection of the upper electrode layers and the lower electrode layers. See, for example, T. Hayashi et. al, “A Novel Stack Capacitor Cell for High Density FeRAM Compossible with CMOS Logic”, IEDM (International Electron Devices Meeting), 2002, session 21.3.
FIGS. 5A-5C show a sectional view illustrating steps of a conventional method for manufacturing a semiconductor device. Further, FIG. 5 is the sectional view taken along a long side of upper electrode layers arrayed in columns. As for a method for manufacturing the cross-point FeRAM, as shown in FIG. 5(A), an interlayer insulating layer 10 is formed by using a known chemical vapor deposition (CVD) on the whole upper surface of a semiconductor substrate (not shown in the drawing) on which a MOS transistor or the like have been provided.
Next, a lower electrode layer forming film (not shown in the drawing), a ferroelectric layer forming film (not shown in the drawing), and an upper electrode supporting layer forming film (not shown in the drawing) can be deposited in this order by using a known sputtering method on the interlayer insulating layer 10. Then, by using a known a photolithography and etching technique, a multilayer for forming a capacitor made up of a lower electrode layer 20A, a ferroelectric layer 20B, an upper electrode supporting layer 20C is provided in multiple numbers in rows in the regions where the lower electrode is formed.
Next, an insulating layer 30 is formed on the whole upper surface of the interlayer insulating layer 10, where the multilayer for forming a capacitor is provided in the regions where the lower electrode layer is formed, by using a known chemical vapor deposition (CVD) method.
Then, as shown in FIG. 5(B), an etching back performs on the whole surface of the insulating layer 30 so as to expose the upper surface of the upper electrode supporting layer 20C in the multilayer for forming a capacitor.
Next, an upper electrode layer forming film (not shown in the drawing) is formed on the whole surface of the insulating layer 30, where the upper surface of the upper electrode supporting layer 20C is exposed, by using a known sputtering method. Then, as shown in FIG. 5(C), by using a known a photolithography and etching technique, an upper electrode layer 20D is provided in multiple numbers in columns in the regions where the upper electrode is to be formed while remaining the upper electrode supporting layer 20C at least in the regions where the upper electrode is to be formed. Here, the etching is performed with a stop at the level of the upper surface of the lower electrode layer 20A. Thus, ferroelectric capacitors can be provided in multiple numbers and each provided at an intersection of the upper electrode layer 20D and the lower electrode layer 20A provided in mulitiple numbers in a matrix.